Hard faults under any conditions are usually difficult to diagnose but imprecise bus faults are especially difficult because the stacked PC and LR are generally unrelated to the error. Memory writes on Cortex M3 can be buffered for several instructions and the fault itself can be postponed if a higher priority interrupt is currently executing. One interesting method to help debug the memory access fault is to disable write buffering. The ARM reference manual describes the Auxiliary Control Register or ACTLR which has a bit (DISDEFWBUF) that disables write buffering. The following code snippet should disable write buffering and make it easier to find the exact instruction that is causing the problem. It may slow down the processor so I would not disable it for normal operation.
uint32_t *ACTLR = (uint32_t *)0xE000E008;<br />*ACTLR = *ACTLR | 2;